Potential application areas for on-chip or highly integrated power supplies include mobile/battery powered devices, microprocessor power supplies, power management for RF transmitters, energy harvesting, etc. This session addresses the key system-level issues brought out by power supply on chip and other power integration techniques. The session will also discuss the requirements, constraints and trade-offs (i.e. performance, cost, complexity) in such systems with a view to defining the potential benefits of power supply integration. Other issues to be discussed will include: suitable input voltages, single or 2-stage conversion, point of load, integration with load.

This session discusses active switching power devices suitable to facilitate various PwrSoC concepts, ranging from traditional BCDMOS to vertical/lateral hybrid devices and SOI RESURF devices. The focus will be on switching frequency from multi-MHz up to radio frequency (RF), process compatibility, and special power electronics requirements such as SOA and energy capability of different CMOS-based device technologies.

Inductors and capacitors are key elements for any DC-DC converter. For power supply on chip, these passive components require novel and improved materials and integration techniques. In particular, multiMHz, soft magnetic materials and high dielectric constant (K) materials are needed to be deposited in a CMOS-compatible technique.

Inductors are key elements for dc-to-dc converters. For power supply on chip, inductors require novel and improved materials and integration techniques. In particular, multi-MHz, soft magnetic materials, deposited in a CMOS-compatible technique, are needed.

The issues to be addressed in this session include:

• Magnetic integration – opportunities and challenges.
• Multi-MHz magnetics – thin film magnetic materials and deposition techniques.
• Material compatibility issues for integration on top of active silicon.
• Achievable power density and efficiency.

Capacitors are fundamentally essential passive devices for any DC-DC converter. For power supply on chip, key measures are energy density, power density, parasitic losses, reliability, and compatibility with standard or emerging fabrication and packaging technologies. In particular, 3-D structures, nano-materials, and otherwise high quality films withhigh dielectric constant (K) and high breakdown field are needed to be deposited in CMOS-compatible techniques. In the case of integration-in-package, more flexibility with materials, processes, and substrates is possible, and solutions that take advantage of such flexibility are of interest.

The issues to be addressed in this session include:

• Silicon compatible capacitor materials and technologies.
• High energy density and high power density capacitor technologies suitable for low-cost co-integration or co-packaging with silicon.
• Magnetic and capacitor integration - opportunities and challenges.

This session addresses power train circuits and controller design for on-chip and other power supplies targeting miniaturization or integration with loads. The session will present the latest advances in converter circuit topologies, including high-frequency, multi-phase or multi-level configurations, resonant power converters operating at RF frequencies, switched-capacitor circuits, topologies that enable ultra-high density miniaturization etc., as well as control systems enabling efficient operation at high frequencies. Light load efficiency issues will also be considered in the context of battery performance in mobile applications.

In conclusion, this session will try to place the power supply on a chip (PwrSoC) in perspective by exploring the entire landscape of power supply integration. Designs and market overview will be presented ranging from “discretes in a package” (PSiP) to “system on a chip” (SoC) in which power supply function is an integral portion of the system. The benefits and the limitations of each level of integration will be explored. Figures of merit will be considered to allow objective integration route characterisation for specific applications. The session will also address issues of performance, efficiency, thermal management, EMC, reliability, cost, flexibility, afforded by the implementations.